1. Field of the Invention
The present invention relates to an auxiliary power source in a battery-powered electronic device, and more particularly to an output stage which generates the auxiliary power from inductive flyback and back emf associated with motor operation.
2. Description of the Prior Art
The back electromotive force (emf) stored in a rotating motor is useful as an auxiliary power supply to power other circuitry in a motor controller, particularly when a collapse in the main supply does not short out the motor and shunt the back emf to ground. Properly protected from a supply short, an auxiliary voltage source powered by the motor may continue for several seconds after a power failure. This valuable time may be used to store information about a systems condition, to initiate some emergency response, to sustain circuitry until a UPS (uninterrupted power supply) can begin stable operation, or to initiate some predetermined shutdown procedure. In a hard disk drive, for example, the back emf from a spindle motor can be used to power a head retract before the disk stops spinning and a head crash results. For such circuitry, it is advantageous for the auxiliary supply to have a voltage even above the battery or input supply voltage.
Common power device technology teaches that parasitic bipolar conduction between a power MOSFET must be prevented by shorting the source and body regions of a MOSFET with a high concentration diffusion and metalized contact. This source-body short results in an intrinsic anti-parallel diode between the source and the drain.
FIGS. 9(a) through 9(d) show section views of push-pull MOSFET halfbridges illustrating the intrinsic anti-parallel diode created by the source-body short. The intrinsic anti-parallel diode is present in both integrated circuits, as shown in FIGS. 9(a) and 9(b), as well as discrete circuits, as shown in FIGS. 9(c) and 9(d).
FIG. 9(a) shows a section view of a totem pole NMOS halfbridge comprising a highside MOSFET 910 and a lowside MOSFET 920. The highside MOSFET 910 includes a p-type well W910 into which are formed an n-type source region S910 connected to an output terminal OUT and an n-type drain region D910 connected to a supply voltage Vcc. The highside MOSFET 910 also includes a high concentration p-type diffusion B910 connected to the source S910 by a metalized contact, thereby creating a source-body short. The source-body short in the highside MOSFET 910 creates a first intrinsic anti-parallel diode 911 between the source/body and the drain D910 of the highside MOSFET 910. The intrinsic anti-parallel diode 911 is back-biased during normal current flow through the highside MOSFET 910, and is forward-biased when the potential at the source/body S910 is greater than the potential at the drain D910. The lowside MOSFET 920 includes a p-type well W920 into which are formed an n-type source region S920 connected to ground and an n-type drain region D920 connected to the output terminal OUT. A body diffusion B920 of the lowside MOSFET 920 is connected to the source S920, thereby creating another source-body short, resulting in a second intrinsic anti-parallel diode 921. The intrinsic anti-parallel diode 921 is forward-biased when the potential on the output terminal OUT falls below ground, and is back-biased at all other times. Note that when the lowside MOSFET 920 is turned-on, current flows to ground regardless of the intrinsic anti-parallel diode 921.
FIG. 9(b) shows a CMOS halfbridge including a highside MOSFET 930 and a lowside MOSFET 940. The highside MOSFET 930 includes an n-type well W930 into which are formed a p-type source region S930 connected to Vcc and a p-type drain region D930 connected to the output terminal OUT. The highside MOSFET 930 also includes a high concentration n-type diffusion B930 connected to the source S930 by a metalized contact, thereby creating a source-body short. The source-body short in the highside MOSFET 930 creates a first intrinsic anti-parallel diode 931 between the source/body and the drain D930. The intrinsic anti-parallel diode 931 is back-biased during normal current flow through the highside MOSFET 930, and is forward-biased when the potential at the drain D930 is greater than the potential at the source S930. Note that when the highside MOSFET 940 is turned-on, current flows from Vcc to the output terminal OUT regardless of the intrinsic anti-parallel diode 931. The lowside MOSFET 940 includes an n-type source region S940 connected to ground and an n-type drain region D940 connected to the output terminal OUT. A p-type body diffusion B940 is connected to the source S940, thereby creating another source-body short, resulting in another intrinsic anti-parallel diode 941. The intrinsic anti-parallel diode 941 is forward-biased when the potential on the output terminal OUT falls below ground, and is back-biased at all other times.
FIGS. 9(c) and 9(d) show that the source-body short, and hence the intrinsic anti-parallel diodes, are an integral part of discrete DMOS designs. The DMOS halfbridge shown in FIG. 9(c) includes a highside MOSFET 950 and a lowside MOSFET 960. The highside MOSFET 950 includes intrinsic anti-parallel diodes 951 and 952 which are back-biased against normal current flow and are forward-biased when the potential on the output terminal OUT is greater than Vcc. In addition, the lowside MOSFET 960 includes intrinsic anti-parallel diodes 961 and 962 which are forward-biased when the potential on the output terminal OUT falls below ground, and are back-biased at all other times. Likewise, the highside MOSFET 970 of the DMOS halfbridge shown in FIG. 9(d) includes intrinsic anti-parallel diodes 971 and 972 which are back-biased against normal current flow and are forward-biased when the potential on the output terminal OUT is greater than Vcc. In addition, the lowside MOSFET 980 includes intrinsic anti-parallel diodes 981 and 982 which are forward-biased when the potential on the output terminal OUT falls below ground, and are back-biased at all other times.
FIGS. 10(a) and 11(a) show two-pole and three-pole driving circuits for driving two- and three-pole motors using the CMOS halfbridge shown in FIG. 9(b). Referring to FIG. 10(a), the two-pole driving circuit includes a first CMOS halfbridge 1010 connected to a first pole of a two-pole motor 1050, and a second CMOS halfbridge 1020 connected to a second pole of the motor 1050. Likewise, the three-pole driving circuit shown in FIG. 11(a) includes a first CMOS halfbridge 1110 connected to a first pole of a two-pole motor 1150, a second CMOS halfbridge 1120 connected to a second pole of the motor 1050, and a third CMOS halfbridge 1130 connected to a third pole of the motor 1050. In each of the CMOS driving circuits shown in FIGS. 10(a) and 11(a), the intrinsic anti-parallel diodes 931 of the highside MOSFETs 930 are back-biased against normal flow of current through the highside MOSFETs 930 and forward-biased when the voltage on the respective pole of the two-pole motor 1050 or the three-pole motor 1150 is higher than Vcc.
Similarly, FIGS. 10(b) and 11(b) show two-pole and three-pole driving circuits for driving two- and three-pole motors using the NMOS halfbridge shown in FIG. 9(a). Referring to FIG. 10(b), the two-pole driving circuit includes a first NMOS halfbridge 1060 connected to a first pole of a two-pole motor 1050, and a second NMOS halfbridge 1070 connected to a second pole of the motor 1050. Likewise, the three-pole driving circuit shown in FIG. 11(b) includes a first NMOS halfbridge 1160 connected to a first pole of a two-pole motor 1150, a second NMOS halfbridge 1170 connected to a second pole of the motor 1150, and a third NMOS halfbridge 1180 connected to a third pole of the motor 1150. In each of the NMOS driving circuits shown in FIGS. 10(b) and 11(b), the intrinsic anti-parallel diodes 911 are back-biased against normal flow of current through the highside MOSFETs 910 and forward-biased when the voltage on the respective pole of the two-pole motor 1050 or the three-pole motor 1150 is higher than Vcc.
FIGS. 12 through 14 illustrate how the intrinsic anti-parallel diodes of the highside MOSFETs in the above-described driving circuits provide an undesirable discharging conduction path from a motor to Vcc, regardless of the device polarity. FIG. 12 show a generalized two-pole driving circuit including highside MOSFETs 1210 and 1220 and lowside MOSFETs 1230 and 1240 which are connected to opposite poles VoutA and VoutB of a two-phase motor 1250. Note that the orientation of the intrinsic anti-parallel diodes 1211, 1221, 1231 and 1241 are the same as both the CMOS driving circuit of FIG. 10(a) and the NMOS driving circuit of FIG. 10(b).
FIGS. 13(a) and 13(b) show flyback pulses generated on VoutA and VoutB during normal operation of the driving circuit of FIG. 12. Each positive-going transition on VoutB generates a flyback pulse having a potential above Vcc which momentarily forward-biases the anti-parallel diode 1221. At the same time, negative-going transitions on VoutA generates a flyback pulse having a potential below ground thereby momentarily forward-biasing the anti-parallel diode 1231. Conversely, positive-going flyback pulses on VoutA momentarily forward-biases the anti-parallel diode 1211, and negative-going flyback pulses on VoutB momentarily forward-biases anti-parallel diode 1241. Each time the highside anti-parallel diodes 1211 and 1221 are forward-biased, the flyback energy is reabsorbed by Vcc.
FIGS. 14(a), 14(b) and 14(c) show how the back emf generated by the motor 1250 is lost to Vcc when the battery fails. At battery failure, the back emf of the motor 1250 (Vemf) is at a level determined by the driving potential Vcc. As Vcc drops to ground, the motor 1250 forward-biases anti-parallel diodes 1211 and 1221 each time a positive-going flyback pulse is applied to either VoutA or VoutB. However, the dead battery (and possibly other energy absorbing circuitry) create a load which discharges the back emf generated by the motor 1250 in about one second or less, which is not long enough to perform emergency power-down procedures.
FIG. 15 shows a prior art method to eliminate the loss of back emf to Vcc after a battery failure, thereby increasing the amount of time Vcc is available for emergency power-down procedures. FIG. 15 includes the generalized two-pole driving circuit of FIG. 12, and in addition includes a Schottky diode 1510 located between the battery (indicated by Vbattery) and the highside MOSFETs 1210 and 1220. The Schottky diode 1510 is forward-biased during normal operation, but when Vbattery fails, the Schottky diode 1510 is back-biased, thereby isolating the back emf generated by the motor 1510 on Vcc. Therefore, Vcc remains at a useful level for a longer period of time, as shown in FIG. 16, and can be used as an auxiliary power source to affect power-down procedures.
A problem with the above-described prior art output stage is that the isolating Schottky diode 1510 consumes significant amounts of power which could otherwise be used to drive the motor and, hence, generate back emf which can be used as an auxiliary power source. It is commonly understood that the voltage drop across a Schottky diode is approximately 0.5 to 1.5 volts. For a 5 volt power source, this represents a power loss of 10 to 30%. Further, because a spindle motor for a hard disk drive draws a current of several amps, approximately a watt of power can be lost due to the Schottky diode 1510, which could otherwise be used for emergency power-down procedures. In addition, in a 3 volt system, even a 0.5 volt diode drop represents a 17% voltage loss which makes the design of control circuitry nearly impossible, especially if a 2.7 volt battery condition is allowed.